??? 07/26/07 13:25 Read: times |
#142340 - a bit iof emphasis Responding to: ???'s previous message |
there are also modes of failure which you won't cover by a simple "logic" test. For example, leaks might develop across the CMOS structure (increased IDD), FLASH retention might suffer, etc. These might lead to various "soft" failures under e.g. marginal voltage (not only high but also low), low temperature etc.
Jan speak of "'soft' failures" what I want to insert is: what if running at 100C for an hour lead to no failure except that something in a the chip get weakened to the extent that the ability to handle ESD get so low that the chip will, some day, blow at the customers site. testing a few specimens tells you nothing on reliability on the long run (e.g. in a new batch etc.) a footnote in the datasheet for the SST39VF1681 states 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. do you need more to substantiate Jan's point. there are more factors leading to IC failure than just simply cooking under maximum voltage. Think of chemicals (mainly moisture), mechanical stress (vibrations and shocks), rapid thermal cycling; and all of these have their long-term implications, too. AND what about the possibility of the chip internally generating a corrosive gas when very hot leading to a lifespan of months instead of eons. All in all, go ahead and do your thing. But do realize it is marketing, not engineering that you propose. Erik |