... all you need, is access to the address bus (that's where the bondout comes in, although different techniques are possible, in the classical '51 world see Metalink), a comparator, a register to hold the address of the instruction where it has to stop, a latch, and a gate on the clock. More sophisticated breakpoints and multiple breakpoints are then only variations on this theme.

Once the core is stopped, it's relatively easy to extract the SFR and RAM content - there is no hurry at that time already.

And, exactly the same is present in the onchip-debug version, only this time it is, ehm, on chip. And, the JTAG comes into play only during the "stoptime".

Trace, once you have access to the internal buses, is only a simple logic analyser. The lack of memory in the onchip-debug ("JTAG") version prevents such features, although there are some tricks to gather that information (e.g. the Versa maintains a so called jump trace, from which you can reconstruct some of the previous run).


Erik and others will please kindly correct me where I was wrong.

JW