| ??? 09/06/07 09:05 Modified: 09/06/07 09:11 Read: times Msg Score: +1 +1 Good Answer/Helpful |
#144076 - during active reset the oscillator is running... Responding to: ???'s previous message |
... hence the power consumption is of the nominal running value (tens of mA rather than a few uA).
The purpose of powerdown mode is to stop the oscillator. JW PS. Actually, after we got the reset circuit producing a proper length output reliably after each powerdown/up cycle (which in itself is not a trivial undertaking, too), this was the other gotcha which remained: we designed in a 2.4V battery (in fact a 2xNiCd accu) as the data retention voltage for the RAM is 2.0V. Now, each spurious reset woke up the '51 but as the voltage was below the minimum operational value (which is IIRC 3.0V), it did not correctly detect "still low power" and go back to powerdown, but it simply went crazy and sucked out the battery completely. |
| Topic | Author | Date |
| Memory of AT89C2051 after reset | 01/01/70 00:00 | |
| this is relatively complicated... | 01/01/70 00:00 | |
| Why no reset during low power? | 01/01/70 00:00 | |
| during active reset the oscillator is running... | 01/01/70 00:00 | |
| power back up? | 01/01/70 00:00 | |
| Oh, certainly... | 01/01/70 00:00 | |
| thanks | 01/01/70 00:00 | |
| alternatives | 01/01/70 00:00 | |
| options? | 01/01/70 00:00 | |
| my way of doing this... | 01/01/70 00:00 | |
| Then jus a RAM chip would work | 01/01/70 00:00 | |
| wouldn't it be easier and safer with serial EEPROM | 01/01/70 00:00 | |
| Maybe | 01/01/70 00:00 | |
| why not FRAM | 01/01/70 00:00 | |
| Combination of Technologies.... | 01/01/70 00:00 | |
| SRAM | 01/01/70 00:00 | |
| I don't think so | 01/01/70 00:00 | |
| this is not matter of "thinking"! | 01/01/70 00:00 | |
| OK, an another gotcha | 01/01/70 00:00 | |
| to Jan | 01/01/70 00:00 | |
| no | 01/01/70 00:00 | |
here is the best chip for u! | 01/01/70 00:00 |