Who's included in that "everybody"? Clearly I'm not, because I've had at least one occasion on which I've observed external bus activity both reading and writing to BBRAM during RESET asserted by a supervisor during the power-down transient. That's at least one case wherein it didn't work properly. They were just ad-hoc observations, however, and not part of a rigorous test setup. I'd bet that it's more than you, yourself, have done. Why did I use the external bus and BBRAM? Well, it's hard to attach 'scope and logic analyzer to the internals, particularly while running at full speed. The BBRAM is supposed to protect itself from runaway processors during power-down. That scheme didn't work so well either.



As I said before, I didn't ask for proof, I asked for observations. Apparently you've made not a one. I suspect if you'd made any observations, and based your assessment on them, you'd have mentioned it by now.

Clearly your work has been based, at least in large part, on guesswork, which, by now, shouldn't surprise anyone. That's why you're so sensitive about this.

It not clear what you mean by "works." Is that 1 unit failure in 3 or in 10, or in 100, and in how many repetitions, and under what conditions?

Have you ever tested anything at all?

BTW, I wouldn't call my remarks a tirade, but, rather, an exhortation to practice sound engineering procedure and to base your conclusions on observation, experimentation, and measurement, and not on conjecture and random guesses.

RE