Yes. I can. I have no much experience with Keil ULINK2 but I can compare true ICE to SiLabs debugger in Keil IDE.
When I started with 51's CPU we used Intel (8" diskettes drive), Nohau and ComAp and now we use iSystem ICE.
All named ICEs have (or had) possibility to trace code and all (some better some worse) have possibility to profile code.

The SiLabs debugger in Keil IDE has no such nice possibility to profile or trace code. If you need to profile time you
have to use oscilloscope (and use free ports = conditional code compilation) or use free PCA (= cond. code compilation too)
or count number of instruction in assembler source code (horrible work). On the other hand it is complex and nice CPU I am sure.

But. The project which initiated this thread has another development demands because we had to document some functions and we
had to use accordant tools with this project. And this way we try to follow it almost in all our projects.

That's why we decided to follow rules mentioned in SCIL-Levels ( ISO Compiler, Style Guide, coding standard as MISRA, VCS,
ICE and so on). And as I siad the SCIL-Level for our project is No. 3.

BTW.: I tried to search the original SCIL draft on the web and I did not find it. But I have it. I am able to
send it the document if you interested and don't have it.

Thank you for your response.
Vaclav.