Wise words indeed Erik. But then, I've come to expect nothing less of you ;o)

I would like to add a few additional remarks:

... design to the data sheets ...
And use a liberal amount of scepticism. Take the max/min values, not the "typical", i.e. worst case design

... mount 100nF ceramic and 4.7uF tantalum DIRECTLY across the uC, 100nF ceramic over all other chips (some may need the tantalum as well) ...
And remember that this is of course no substitute for a proper Power/GND layout! When working with todays high-speed CMOS circuits, a low-impedance GND connection is essential. If at all possible you should use a solid (that is: having no other gaps than the ones necessary to accomodate the device pads) groundplane and preferably a Powerplane as well, though this will usually require a multilayer PCB.


Have fun,
On a Saturday? Really, Erik! LOL

Have a great weekend,
Rob.