hat I want to implement is known as a pulse programmer. I need to generate a pulse train of three or more pulses of different duration and varying delays in between.

For the current application I need three Pulses of following specifications.

Pulse 1- 0.1 microSec to 99.0 microSec
delay 1 (between first and second pulse) 100 microSec to 100miliSec
Pulse 2- 0.1 microSec to 50.0 microSec
delay 2 ( between second and third pulse) 0.1 microSec to 99.0 microSec
pulse 3- 0.1 microSec to 99.0 microSec
delay 3 ( between third and first pulse) 10 mili Sec to 100 sec

I tried this with a AT89S8252 and a Intel 8254-A ( 10 Mhz one) but the counter timer chip got very hot at 10 Mhz and I had to abandon the idea. Using descrete logic it will take more than 100 TTL or CMOS ICs and a lot of wiring and debugging.

I have some idea of FPGAs and CPLDs but unfortunately the VHDL programming can take months for me to learn and implement.

The commercial equipment costs a fortune and sadly out of reach of us.


the problem seems to be able to generate accurate and reliable and controllable delays of 0.1 to 5 microsec the bigger delays are not so difficult.
Using NOPS and jumps i can generate delays of sufficient accuracy but what about the JB and JNB, JNZ ,JZ which have a variable time duration of execution. and they are needed to implement a delay.


I need some help guys.
Need any more detail??

vinod