I too have used SRAMS in this manner. An SRAM with a counter on the address lines and a edge triggered latch on the output can make an excellent solution to this type of "arbitratry waveform" generator. It seems that it would also be easy to provide the processor with the ability to clock the address counter under software control, and a port and -WR control line to load the data into the SRAM.

I would design the SRAM structure to run a single shot sequence of the timing and then have a PCA or TMR2 output from the microcontroller trigger the repeat times. This will make it be fairly feasible to each the broad range of repetition times that he wants. Even a carefully designed software timing interrupt with latency equalizer could be used to re-trigger the single shot run of the counter.

Using a 32Kx8 SRAM would permit a single shot timing sequence of 32768 x 100 nsec = 3276800 nsec = 3276.8 microseconds = 3.2768 milliseconds duration. A 256K byte part would provide 4 times longer duration at 13.10 milliseconds.

If one were to take a somewhat brute force approach to Vinod's pulse specifications and use an overall 100 nsec resolution for the counters then if we look at his maximum periods for a single shot sequence:

      990  (counts @100 nsec - 99 usec max)
  1000000  (counts @100 nsec -100 msec max)
      500  (counts @100 nsec - 50 usec max)
      990  (counts @100 nsec - 99 usec max)
  +   990  (counts @100 nsec - 99 usec max)
  --------
  1003470

...you can see that an SRAM that was a megabyte deep would be required to implement the timing sequencer. Depenging on the cost profile that Vinod requires for his product the use of a 1MByte SRAM may be too expensive. There is a scheme that can be used, (with careful synchronous logic design of course), where by a number of the extra bits of the SRAM output can be used to feedback and select a new prescaler selector for the clock that drives the counter. Thus the timing resolution of the clocking to the SRAM can be changed on the fly to conserve on the amount of SRAM used.

The block diagram below shows how this could be configured.


A final comment is that a smallish sized CPLD would make an excellent choice for encapsulating the address counter, the output register, and the clocking prescaler logic.

Michael Karas