The problem board gets its clock from the "master" controller board. The controller board directly controls the operator interface board that operates flawlessly (it always reads the keypad output and reflects the system state via an LCD correctly). The clock signal waveform is the same for both boards (I checked using a scope). The controller on the "problem" board is good to 24 MHz (I replaced one that topped off at about 16 MHz I think).

I verified the clock specs for both chips and the 4 MHz clock (from a can) is well within spec. The problem exists with a 12 MHz clock too. When I probe the input to the latches and the wr' line is active, the data presented equals that of the DPL and not the data loaded into the Accumulator. To recap: an enable to a latch is the combination of the inverted wr' signal and one of the P2 lines (I have five latches so P2.1, 2, 3, 4, and 5 are used for this purpose). These appear to be in sync with the enables appearing at the latch inputs.

Something simple is wrong and I am having a devil of a time finding it. The problem with things like this is that you who are trying to help can't see my board to verify for yourself that the logic is implemented properly. I really appreciate your thoughts and think that this forum is a very good thing. At least I know I'm not alone.

Thanks, Jeff Biss