Hi Jeffery,

> To recap: an enable to a latch is the
> combination of the inverted wr' signal and one of the P2
> lines (I have five latches so P2.1

Its a little vague.

So let me clarify it:
E.g. you use a 74LS373 latch, which was transparent on high level on the enable input.
Then you must combine the /WR with P2.1 over a NOR (74LS02) gate.
So, if /WR and P2.1 are low at the same time, the enable pin was high and the data was written into the latch.


Peter