You summed up the discussion. OK there need not be a discussion as to why one should use it. But can you just enlighten which type is better for this purpose - Tantalum, Disc ceramic etc ?

In fact I have seen most data sheets from Analog Devices showing another 10 mfd in parallel with the 100 nf capacitor. If AD recommends something then better follow it.

And if space is a constraint, why not use the IC bases that have the 100nfd built into them - assumin you use bases.

Dear Raghunathan,

the worst enemy of every decoupling measure is 'inductivity'! So, everything that minimizes this 'unavoidable' inductivity will greatly help.
It's not so much the inductivity of decoupling capacitor itself, which counts. Although in GHz applications even the inductivity of terminal wires are too high and only an SMD version can be used. It's more the inductivity of copper traces from decoupling capacitor to pins of chip!!!
Concreteley spoken, there are two connections: One from decoupling capacitor to 0V pin and one from decoupling capactor to Vcc pin. Both play the same role, of course, and the whole length is what must be taken into account.
But, there's nevertheless a difference: If your PCB contains a solid ground plane, inductivity of ground connection of decoupling capacitor can always be made much, much smaller than connection to Vcc pin. This is mostly valid, when using single sided PCB, where a solid ground plane or at least very wide ground traces are used. Or, when double sided PCB are used, where one side contains the solid ground plane.
When you use multilayer PCB, then there will mostly be a solid ground plane and a solid Vcc plane. Then inductivity of Vcc connections can also be minimized.

So, if you use PCB design containing only solid groundplane, it's wise to locate decoupling capacitor as close as possible to Vcc pin. Then connection to Vcc pin shows minimum inductivity.
On the other hand, connection from 0V pin of chip to decoupling capacitor is longer, of course, but profits of low inductivity of solid ground plane, or at least very wide ground copper traces.

Let's have some example:
If you have to decouple DIL40 package, then total connection length of decoupling capacitor to Vcc and 0V pins is about 5cm. Piece of wire of this length makes about 50nH of inductivity, according to rule of thumb: 1nH/mm. Compared to equivalent series inductivity of a good decoupling capacitor (with wires) of about 5nH, you see that inductivity of length of connections is highly dominating. So, when using an unproper connection between decoupling capacitor and Vcc and 0V pins of chip, then even the best type of decoupling capacitor cannot remove inductivity.
50nH inductivity corresponds to a thin wire of 5cm length, but also to a narrow copper trace of same length. Only by using solid ground plane this inductivity can highly reduced!!

So, you see, it's not only the decoupling capacitor technology which counts but also the way how the decoupling capacitor is connected to chip. Even an SMD capacitor with 1nH equivalent series inductivity can not help, if solid ground plane is neglected!!!!

In this context use of 'in the socket built-in' decoupling capacitor is not so good, friendly spoken. Because the advantage of low inductivity of solid ground plane is wasted.

I remember a development, where I wanted to use 74HC4046 (PLL) and I had problems with jitter of VCO. I connected 100nF decoupling capacitor (type with wires) directly across Vcc and 0V pins. But to my surprise supply voltage ripple was terrible high. Then I soldered directly across decoupling capacitor a second one, but in such a way, that its leads were not also fed to pins of chip, so that still only one wire was going to each pin. No change of ripple!
Then I removed this second capacitor and soldered a new one, but in such a way, that also its leads were fed to package pins. Do you understand? Then riplle was halved!! Why?
Because the second set of wires halved the inductivity!

This demonstrated, that not the inductivity of decoupling capacitor was the cause of ripple, but the thin wires making the connection to chip pins. And the only way to heavily reduce this inductivity is to use solid ground plane. You will be surprised to see, how much the ripple can be reduced, when using solid ground plane and locating decoupling capacitor as close as possible to Vcc pin!

What types of decoupling capacitors to use?
I take 100nF/50V X7R cearmics in 0805 SMD package for decoupling purpose. And I locate them at each chip very close to Vcc pin. I try to realize a solid ground plane ranging at least from 0V pin of chip to decoupling capacitor.
I don't like sockets and I use them only for PLCC micros or whenever I must take a selected chip, like ADC with proven specifications. But most the time I use SMD packages soldered directly on double sided PCB. (This can even be done with standard soldering iron.)

I know of some people using SMD tantals of about 2.2µF instead of 100nF/X7R. This will also work in most cases.

Parallel combinations of decoupling capacitors are often used, when impedances of less than 1Ohm is needed for frequencies much lower than 1MHz, so, often for analog chips. Then, obligatory 100nF/X7R can be paralleled by a tantal or aluminium electrolytic. But selecting values must be done carefully: Electrolytic capacitor must not have equivalent series resistance of less than about 0.5Ohm arround 1MHz, otherwise impedance of parallel combination will show some resonance peak. This can be calculated AND verified with a good scope...
Good combinations with 100nF/X7R (0805 package) are: 10µF/63V, 22µF/50V, 47µF/35V, 100µF/25V all standard aluminium electrolytic. If tantals are used, bigger values than 10µF can make trouble. Good combinations are 100nF/X7R + 2.2µ/10V...10µF/6.3V tantals.
On the other hand, impedance maximum is to be expexted, when paralleling electrolytics by ceramic capacitors of much smaller capacitances than 100nF.

Paralleling of decoupling capacitors is also necessary, when LC-filters are used, means if a ferrite bead is needed to increase dampening. In combination with 100nF/X7R only, heavy ringing would occur! It can be shown, that for avoiding ringing the following criteria must be fullfilled:

R >= SQRT (2 x L / C)

Where R is series resistance, L inductivity of ferrite bead and C is decoupling capacitance. If you use BL02RN2 ferrite bead (murata) about 2.2µH in the low MHz range is to be expected. In combination with 100nF/X7R formula yields R >= 6.6Ohm. If you do not insert a resistor of about 6.8Ohm, then ringing at 1 / (2 x pi x SQRT (L x C)) = 340kHz will occur.
But if you parallel 22µF/25V electrolytic formula yields R >= 0.4Ohm. And because equivalent series resistance of electrolytic is in the range of about 1Ohm, you even need no additional resistor to prevent ringing!! This technique yields high efficient decoupling and power supply filtering. Corner frequency of filter is about 23kHz.

Kai