Hi Rob


Do you intend to use the hot airgun method as advocated by some on the Si-labs forum..
Also.. The minimum DRC I work to for track spacing and width is 10thou (keeps cost down)... Does the pad/track spacings on the CP2101 fit within my rules..

The publication Michael pointed to is quite scary.. I can manage PLCC,TSSOP,QFP,SQFP,TQFP , but some of the newer packages may make chips unuable for most people.

How long before they just ship the wafer?..