Hey Charles,

Are you familiar with the PLL method of dividing the output frequency of a clock signal? I know this can be done, but I've never looked into just how it is done. If you, or anyone else for that matter, know(s) could you give a sort of quick and intuitive description of how it is done? Could it be done with an 8051 or derivative, and if so would it require that the µ-controller be dedicated to that function only?

The only time I've ever looked at a PLL it was regarding the tuner circuit on a receiver, and it was very much analog. Moreover, like you, if I were trying to build a variable frequency output my first iteration would likely be analog too. Nonetheless, I suspect that if I knew how it was done digitally I might prefer the approach, or at least would be able to make an intelligent choice.