??? 04/15/04 22:11 Read: times |
#68589 - RE: Changing Clock f while chip is runni Responding to: ???'s previous message |
Hello Charles,
Although I tend to agree with you that PLLs are "really neat", the design of them is certainly a lot more involved than you make it sound. Things like stability, jitter, settling time and noise all conspire to make life a misery for the hapless designer. A lot of good stuff on the design of PLLs can be found at: http://www.circuitsage.com/pll.html By the way: Arguably the most beautiful thing in this world is digital in nature! Best regards, Rob Klein. |