Hallo Joe,

I had a look into datasheet of DN2540 and found out, that if soldered on a 25mm x 25mm copper area (FR4) SMD package would withstand up to 1.6W at Ta = 25°C. As in my estimation only about 0.95W has to be dissapated, and this only if actually 50mA are flowing, which is very conservative, I don't see any problem with DN2540. May be you have to increase the copper area, where the FET is soldered on, a bit.

Even the trimmer might be avoided if some preselection is done. I know, people today do not preselect any more, like it was the case some fine years ago. But may be you can find out a fix resistor value, where 90%, or so, of DN2540 types will work??
But if this little trimmer is really a problem, which I cannot believe, then a bipolar current limiter can be chosen. But then slightly higher voltage drops must be tolerated. What is minimum compliance voltage of your current sources?

I have drawn a little schematic to demonstrate how I would manage the situation, if I had to find a solution with as few as possible changes:



You see I added bidirectional transzorbs SMBJ30C (SMD style) at inputs. This makes the circuit extremly robust. Now the LL4148 (next to DN2540), DN2540 and INA128 are surely protected. I also added an unidirectional transzorb across trimmer. By this, Ugs will never be exceeded. This is important, because internal parasitic gate source junctions often work like a thyristor, which results in total destroying of the FET, if once gate source voltage is overranged.

Between the two current terminals '+I' and '-I/0V' I added an overvoltage detection circuit, which is optional, of course. Whenever this 24V is connected eroneously, causing the current limiter to invoke, detector circuit will flash a LED. Here an unidirectional transzorb, working as a high power zene dioder, sets a threshold of about 17V. Only if the voltage across the two current terminals is higher than this threshold, LED is able to flash.

At input of INA128 I have reduced the value of capacitors to 10nF. This will help to keep the 'symmetry' high and by this to enhance common mode rejection ratio at low frequencies of about 50...60Hz (mains hum!).
Of course, as I told in the former posts, a true instrumentation amplifier design, providing identical, means symmetrical load impedances would give much higher common mode rejection ratio. But unfortunately best performance can only be achieved, when at the same time signal sources provide true differential outputs, which is not the case in your application, I guess. So, when using your concept, you always must accept a certain loss of common mode rejection ratio.

But your application shows one important advantage, which allows you to improve common mode rejection again. I noticed, that R1, C8 (140k, 100n) provide a low pass filter with corner frequency of about 11.4Hz. This will reduce mains hum and their harmonics!
If you still suffer from poor common mode rejection ratio you can easily improve this low pass filter, for instance by exchanging it by an active, two pole filter. Of course, this does not increase common mode rejection ratio at frequencies below 12Hz. But common mode interference mostly comes with 50/60Hz and higher frequencies.

Kai