I have a few questions about the circuit if you would be so kind to enhance my knowledge.

1)Consering the 100R trimmer how is that adjusted? How does someone know when it is properly adjusted? Perhaps I am missing something but it is not clear to me how someone would adjust this and know it is set correctly. How is the current limiting calculated is that dependant upon the Rds on value of the FET?

Have look at this figures, which can be found in datasheet of DN2540:



The 100R trimmer serves the function, that all the current flowing through the MOSFET DN2540, means drain source current Ids, ALSO flows through the trimmer and forces a voltage drop, which is identical to gate source voltage Ugs! Assume the trimmer is adjusted to 30R. Then Ids of 0.1A would cause a voltage drop across it of 0.1A x 30Ohm = 3V, which automatically forces Ugs to be -3V. Or by other words: If once the trimmer is adjusted to 30R, Ids = 0.1A would force a Ugs of -3V.
Now we can ask: Is this pair, namely Ids = 0.1A and Ugs = -3V, allowed by the datasheet?
No, it isn't! We don't find any Uds, where at Ugs = -3V a current of Ids = 0.1A can flow through DN2540.
If we want to have a current of Ids = 0.1A to flow, we must provide a gate source voltage of about Ugs = -0.55V. We see also from above figures, that Uds must be greater than 3.5V.

What does this mean?
It's not possible, that a current of Ids = 0.1A can flow, if we adjust the trimmer to 30R!! Because the resulting Ugs, forced by the voltage drop of this current across trimmer, does not allow this.

Now, let's discuss another current. Let Ids = 10mA. Can this current flow, with trimmer adjusted to 30R?
Voltage drop across trimmer would then be 10mA x 30Ohm = 0.3V. So, this would correspond to Ugs = -0.3V. And from above figures we see, that this is an allowed pair. More, we can see what the voltage drop across drain source channel would be: Uds = 0.2V.

Ids = 20mA would result in: Ugs = -0.6V, Uds = 0.5V.

Ids = 0mA would result in: Ugs= 0V, Uds = 0V.

What would be the maximum current, that is allowed to flow through DN2540?
About Ids = 30mA. This would cause about Ugs = -0.9V and Uds = 1.0V. Bigger Ids currents result in gate source voltages which does not allow the flow of these currents. But smaller Ids currents can flow without any problems.

There are two major disadvantages with this clever circuitry:

1. FETs can show drastical manufacturing tolerances. An adjusting procedure is mostly necessary.

2. There's some temperature dependency with this mechanism. Means, if the MOSFET heats up, because the limiting mechanism was invoked, adjusted maximum current can drift away by about 10...20%. This depends on actual overheating and cooling, of course, and cannot be predicted into total detail. So, copper area, where this SMD FET is soldered on should be chosen large enough.

How to adjust the current limiter?
First set trimmer to maximum value. Then apply 24V. Measure voltage drop across shunt resistance (100Ohm in your application). Now decrease resistance of trimmer up to the moment, when this voltage reaches 3V, which means a current of 30mA. Check the voltage drop for some time, while the MOSFET is heating up. It should not change more than about 20%. If this is violated, then provide better cooling for the MOSFET.

By the way, this is part of developing phasis. May be, the cooling must be improved drastically, may by DN2540 shows too high temperature dependeny, may be BSP 149 is a better choice, may be trimmer must be increased to 250Ohm, because tolerances of MOSFET are too high, may be, may be, may be... Only a careful development can clearify these questions, but not me here at the clean table.

2)Is there a quantative value you can put on how much this circuit improves the common mode compared to the original circuit? Was the old one limited to 2.26V common mode because of the fixed inputs of Q2 and U8 and this one is higher?

'Common mode' is not fully. There's 'common mode input voltage range' and common mode rejection ratio'. The original circuit, you posted, did not provide any relevant common mode input voltage range. Here I mean common mode voltage as that kind of interference, which is superimposed to regular signal voltage or voltage drop across shunt resistor. This makes sense, because your circuit does not provide true differential signal capability. So, if 20mA curent is flowing, then only +0.26V common mode voltage is allowed to be superimposed. If signal voltage is zero, then common mode input voltage of only about -0.2V is allowed by U8 (OPA237).
So, yes, it's the current limiter section arround U8, which forbidds any relavant common mode input voltage. The modificated circuit does allow a common mode input voltage of at least +-3V. Even higher positive common mode input voltages can be accepted, but as common mode interference is nearly always AC style, not DC, an unsymmetrical specification would not make much sense. If the INA128 would be powered by a more negative supply voltage, even much higher common mode input voltages, positive and negative ones could be accepted by the circuit!

You have an LED when 24V is applied. Would it be possible if an LED would illuminate when the common mode voltage was getting above an area when the circuit would not function properly or errors would be expected?

Yes, have a look at here:



TLC352 would make the job.

3)CE compliance is a must for this product and I noticed that you did not include the ferrite beads in your schematic. Are they not necessary with the transorbs or should they be put on in the front end?

This highly depends on your layout and your grounding and shielding methode. The transzorbs and capacitors directly at inputs will heavily decrease danger of ESD events. And these capacitors will also minimize radiation. But if you want to improve this, you are free to add some ferrites. A PI-filter arrangement would be appropriate. Have a look at the following post by Michael Karas:

http://www.8052.com/forum/read.phtml?id=52259

It will demonstrate, where to put the grounds of involved filtering parts. But again, this CE stuff cannot be discussed without having any idea about used layout, shielding concept and grounding methode.

4)This is kind of a side question. I am wondering how is the voltage calculated to the INA128 when 0 - 5 and 0 - 10 Volts is applied? When it is 4 - 20 mA the 200 ohm shunted resistors would give an input of 0.4 V to 2.0 V. How is that calculated when using a voltage input?

The two 10kOhm resistors at noninverting input of INA128 will divide input voltage by a factor of about 2. But, being exactly also the shunt resistor must be taken into account. Input voltage is divided by the factor: (10kOhm + 10kOhm +100Ohm) / (10kOhm + 100Ohm) = 1.9900990. So, 5.000V at cable input gives 2.512V at input of INA128.

5) How can common mode rejection ratio be tested on the bench?

Short circuit '+I' and '-I/0V' inputs. Apply a voltage to this connection, while 0V of this voltage is connected to 0V of circuit. This gives you true common mode input voltage. You can use a sinus generator, producing 1Veff for fabricating this common mode voltage (Uin). If you wobble through the frequency range of interest (0Hz...10kHz) and measure the resulting nonvanishing rest of this common mode input voltage at output of INA128 (Uout), you can find the common mode rejection ratio as:

CMRR[dB] = 20 x lg (Uin / Uout)

The same has to be done with +'V' and '-I/0V' inputs, of course.
But again, as your circuit does not provide true differnetial inputs and your signal sources does not provide true differential outputs, this above gained CMRR specification is not really valid. Think for instance about the source impedance of signal source, which is very probably different for actual signal line and ground line. This must be taken into consideration.

How is the circuit changed into a two pole active filter and why would you not want to do this?

Have a look above. Low pass filter arround TLC277 provides about third order Bessel characteristic, with same corner frequency as original circuit.
I would use this sophisticated filter, if potential violation of Shannon-Nyquist theorem is an issue. Also, if common mode interference is high.

Kai