Dear Oleg:
Hello, I did what you asked with a T89C51RB2
The configuration was:
XTAL = 18.432 MHz
SR0= 1
SR1= 0 => BD = 64
SR2= 1
X2= 0
Reading with oscilloscope was 145.8 KHz

SR0= 1
SR1= 0 => BD = 64
SR2= 1
X2= 1
SPIX2= 0
Reading with oscilloscope was 291.6 KHz

I guess your simulator is right, nor datasheet is wrong. If you check datasheet page 11 of T89C51RB2 there is a diagram that explains when X2 bit is on XTAL frequency directly feeds to CPU & peripherals. Of course CPU needs 6 Clock per cycle but SPI clock generator doesn’t, it dosn’t divide it to 6 but divide the Fclk periph to BD which is specified in SPCON. Check also page 10 of datasheet, it explains that in X2 mode Fclk periph = Fosc.

Best regards
Reza Fallahati