hi,

Okay, I will try explain from other side.
For Atmel devices which support X2 mode, there are CKCON registers for control X2 mode of built-in peripheral.
Yes, you are right: the each peripheral has own pre-divider. For example, timer 0 is clocked with divider 1:6 or 1:12 depend on bit T0X2 of CKCON0. It is because the timer has divider 1:6 on its input and additional divider 1:2 is controlled with corresponded bit of CKCON0 register (together with master bit X2 of course). And so datasheet says: "Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle."

It all is clean for timers. Now we look at SPI. Datasheet says that there are three Serial Peripheral Rate bits which control SPI input clock pre-divider. With these bits we may select pre-divider in range 1:2...1:128.
It is good for now. Now here is trouble.
There is bit SPIX2 in CKCON1 register. Logically, it just add/eject additional divider 1:2 like for timers. As result it modifyes total divider to 1:4...1:256. But why does datasheet says about this bit the same: "Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle." Where are here 1:6 or 1:12 - such dividers are nop possible for SPI.
I think that it is just "copy-paste" bug in datasheet. Yet another "present" from Atmel.

Regards,
Oleg