hi,

Of course CPU needs 6 Clock per cycle but SPI clock generator doesn’t, it dosn’t divide it to 6 but divide the Fclk periph to BD which is specified in SPCON.

Sure? Okay, now read page 14 what it says about bit SPIX2 (bit 0 of CKCON1 register):

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SPIX2
SPI Clock control bit.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
---

And now answer: what does this bit control?

Thanks,
Oleg