Dear Oleg,
Hello, now I see the reason of your confusion. RD2 datasheet as well as RB2 datasheet both indicating that SPIX2 bit is placed in CKCON1 (SFR 0xAF) and CKCON0 bit 7 is reserved but surprisingly in the document referred by you it says firmly (graphically!) that CKCON0 bit 7 is SPIX2 and it says nothing about CKCON1 !!!
As I said earlier I couldn’t find any official document from atmel explaining exact role of SPIX2 but in X2 datasheets there is a paragraph that says

This paragraph seems very confusing to me too what does they mean 12 clock periods per peripheral clock cycle and 6 clock periods per peripheral clock cycle
I don’t know is it because of my poor English or because of a terminology that I’m unfamiliar with (it would be much appreciated if our friend mr.andy neil with his precise terminology would check this sentences and would tell us if it is right) but I interpret above sentences as you did in your previous post that for each 6 or 12 periods of master clock if you like, there will be one clock for the peripherals. In other words master clock is divided to 6 or 12 for peripheral but not for CPU (please consider that this has nothing to do with prescalar divider). This is in sharp contrast with what has been said in page 16 of the same datasheet (AT89C51RD2) and with my brain logic. In page 16 of AT89C51RD2 datasheet (or page 10 of T89C51RB2) it is graphically stressed that peripheral clock will be the same with Oscillator frequency if X2 bit is enabled and CKRL is 0xFF !!!
But throwing away the datasheets and back to the real world of trail and error ! I I got the results that I posted earlier. Please consider for turning on or off SPIX2 I wrote 1 or 0 to SFR 0xAF not to bit 7 SFR 0x8F and I reached to that conclusion that SPIX2 is a divider by 2 which divides peripheral clock(which is equal to oscillator frequency in X2 mode) by 2 when it is on.
If you really need that, I can write to bit 7 SFR 0x8F to see what happens otherwise I will do it later to just satisfy my curiosity!

Best regards
Reza