In the case of any vhdl code which I submit I will include a suitable test bench where its applicable.I am just now working on putting together a package for the long overdue sdram controller which I promised some time ago.You'll be pleased to hear that there are two versions one which works with single read/writes and the other does paged read/writes with page long asyncronous fifo on the fpga.It has been used with the simulation models of micron sdrams
www.micron.com/dramds
But the test bench suffers from the usual problems of excessivly long simulation times which everyone moans about.