The circuit that is used to control this is two flip-flops (aka f/f) and some logic gates. The first f/f is used to latch the data to the port and needs to be there anyway. Its clocked by a WR/ into the "port cell" (the name we give to the logic around the port and the drive FETs). The output of this first f/f is also connected as the input to a second f/f also clocked by the WR/ signal to the port. Thus the first f/f always has the current state and the second the previous state. The its a simple counter to count 2 clocks. Why not also do 2 clocks when the previous state was a 1 and the current state is a 1? When an 8051 port is used as an INPUT, you need to write a one to the port.If you wrote a zero, the strong n-channel pulldown will not allow an external circuit to drive the pin high unless you source a huge amount of current INTO the port pin - probably on the order of 40 mA or more. By writing a one, the external circuit can pull the pin low by sinking the source current of the internal pullup. The spec for the max you need to sink is -650 uA. Both the weak and medium pullups are on. When the pin falls to about 40% of Vdd, the medium pullup is turned off and you only need to sink about 50 uA. The purpose of this is to reduce your overall system current when you drive pins low. Now since you had to write a one to a pin to use it as an input, if a "was a one, now is a one" condition caused the strong pullup to be on for 2 clock cycles every time you wrote to the port, you would end up with the external devices that are trying to drive inputs in your system needing to sink a lot of current everytime you manipulated a pin on the port or wrote to the port. Remember that bit operations on ports are internally performed as byte writes to the port.