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02/18/05 23:36
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#87922 - JTAG question
Some time ago Ashish Pradhan posted a message about a Cygnal micro responding differently whether or not the IDE was connected to the chip via the JTAG.

I have just run into to the same problem with a F236 which shares a common SPI network with 2 other Cygnal chips 06 and 120
as well as a Motorola 5272.

On some boards, the SPI communication between the 236 and the 5272 quits if the IDE is not runnning. Everything works fine under the IDE. If I power down and up again (without touching the JTAG connector)I appear to get quite unreliable SPI transfers. I don't think it is a grounding problem since I have not removed the JTAG connector at any stage.

I have a logic analyser looking at the outbound lines from the 5272 and some test ports on the 236 that should become active during the SPI transfer and while some other functions in the 236 code are being executed. The 236 simply does not seem to respond.

Yet on the board I did the original development, identical I think to the problem boards, I saw no such problem. I suspect a timing problem but have not been able yet to verify this.

Ashish, did you find a solution to your problems?

John Robbins.


List of 19 messages in thread
TopicAuthorDate
JTAG question            01/01/70 00:00      
   re:            01/01/70 00:00      
      Re:JTAG            01/01/70 00:00      
         Stop!!            01/01/70 00:00      
         Not even a question!!            01/01/70 00:00      
            Re:JTAG            01/01/70 00:00      
               Another thing...            01/01/70 00:00      
                  Re:JTAG            01/01/70 00:00      
                     Reset generators`            01/01/70 00:00      
                        SC-70-3 Reset Circuits            01/01/70 00:00      
                  mandatory            01/01/70 00:00      
                     Re:JTAG            01/01/70 00:00      
                        Which all goes to show...            01/01/70 00:00      
            reset supervisor            01/01/70 00:00      
   Re:JTAG            01/01/70 00:00      
      correct, but            01/01/70 00:00      
         Re:JTAG            01/01/70 00:00      
            yes, but            01/01/70 00:00      
               Re:JTAG            01/01/70 00:00      

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