| ??? 02/22/05 22:33 Read: times |
#88190 - correct, but Responding to: ???'s previous message |
Concerning the need for an external reset supervisor IC, I checked with Silabs support who indicated that this is not generally necessary since the Silabs chips contain a VDD monitor which is enabled by setting the MONEN pin high.
Absolutely correct, but when you employ multiple processors all kinds of strange things can happen if they do not come out of reset simultaneously. Any single SILabs processor board I have use the internal suprevisor, every multiple processor product I have use an external reset. Erik |
| Topic | Author | Date |
| JTAG question | 01/01/70 00:00 | |
| re: | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| Stop!! | 01/01/70 00:00 | |
| Not even a question!! | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| Another thing... | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| Reset generators` | 01/01/70 00:00 | |
| SC-70-3 Reset Circuits | 01/01/70 00:00 | |
| mandatory | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| Which all goes to show... | 01/01/70 00:00 | |
reset supervisor | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| correct, but | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| yes, but | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 |