| ??? 02/19/05 23:38 Read: times |
#87985 - Re:JTAG Responding to: ???'s previous message |
Michael,
Thank you for your vigorous response. We have been using Cygnal chips for 3 or 4 years now and this is the first time we have had this type of problem, so I guess we have been lulled into complacency. I am still not sure that the reset line is the cause of the problem but in any case we will certainly start using reset supervisors. Any other suggestions for the observed problem would be gratefully received, ie differing peformance whether or not the IDE was running. John |
| Topic | Author | Date |
| JTAG question | 01/01/70 00:00 | |
| re: | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| Stop!! | 01/01/70 00:00 | |
| Not even a question!! | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| Another thing... | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| Reset generators` | 01/01/70 00:00 | |
| SC-70-3 Reset Circuits | 01/01/70 00:00 | |
| mandatory | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| Which all goes to show... | 01/01/70 00:00 | |
reset supervisor | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| correct, but | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 | |
| yes, but | 01/01/70 00:00 | |
| Re:JTAG | 01/01/70 00:00 |