??? 02/20/05 14:43 Read: times |
#88006 - Re:JTAG Responding to: ???'s previous message |
We took a lot of trouble with the 4 layer PCB design including adding bypass capacitors next to all power pins in the same fashion as your link shows. For the mixed signal ICs we partitioned analog and digital ground and power planes under the chip towards the side with all the analog pins.
I added a couple of tie points between the analog and ground power planes as I was not sure where the optimum common point would be. In the first couple of boards made, we forgot about putting in the ties and the resulting ground bounce immediately fried the F060 but not if I remember rightly the F120. John Robbins |
Topic | Author | Date |
JTAG question | 01/01/70 00:00 | |
re: | 01/01/70 00:00 | |
Re:JTAG | 01/01/70 00:00 | |
Stop!! | 01/01/70 00:00 | |
Not even a question!! | 01/01/70 00:00 | |
Re:JTAG | 01/01/70 00:00 | |
Another thing... | 01/01/70 00:00 | |
Re:JTAG | 01/01/70 00:00 | |
Reset generators` | 01/01/70 00:00 | |
SC-70-3 Reset Circuits | 01/01/70 00:00 | |
mandatory | 01/01/70 00:00 | |
Re:JTAG | 01/01/70 00:00 | |
Which all goes to show... | 01/01/70 00:00 | |
reset supervisor![]() | 01/01/70 00:00 | |
Re:JTAG | 01/01/70 00:00 | |
correct, but | 01/01/70 00:00 | |
Re:JTAG | 01/01/70 00:00 | |
yes, but | 01/01/70 00:00 | |
Re:JTAG | 01/01/70 00:00 |