His solution is bullet-proof (no accumulating error), as long as one condition is met: there must be always be at least one sample between the edges. This condition is met, if the "plateau" (clear of any transition) between the edges is long enough (> period of sampling) - this is given by the encoder rotation speed and its construction.

This has nothing to do with the frequency of eventual oscillation when the encoder stops at an edge; this can be arbitrarily high or low. The fact of periodical sampling together with the existence of the "clean areas" is the filtering itself.

Note, that it is sampled by a periodical clock, not the inputs' edges - Peter stressed this.


For example, let the encoder stay between state 1 and 2. It has seen state 1 at the last moment of sampling. It the next sampling sees state 2, OK, let it be 2. If the next is 1 again, OK, let it be 1. And so forth, until the encoder starts moving. The design ensures, there is at least one sample in the "clear" area, either 1 or 2, depending on the direction of the movement. And so it does not lose a single step. The only uncertainty is the +- 1 step while it is sitting at the edge wiggling, this error is not accumulating.

Of course, anything similar in CPLD/FPGA/DSP/silicon will work, too.

Jan Waclawek

PS. Sorry, I am not able to read vhdl so I don't understand, how Jez's solution works - is it similar or not.