Wel the way the hardware works is it has a filter both the inputs which consist of a shift register and a detector to determine if its had three samples the same,the filter output gets set high or low when there are three samples of the same value in the shift register

The output of the filter then gets fed into a state machine which looks at the two inputs and determines the direction of rotation and the speed and is sampled at the nominal clock frequency,and a counter gets incremented or decremented according to the rotation direction.The counter gets incremented or decremented on each transistion so the input going from a=1,b=1 to a=1 b=0 counts as a transiston.The counter is 16 bits wide so the sel input drives a mux to select either high or low byte output.

I just for the hell of it synthesised it into an altera cpld and the static timing gives 42 Mhz as the highest clock speed for the path from the clock input to the up-down counter.