How much the ground return current in the ground plane will be 'concentrated' under the signal copper trace can be estimated by the 'coupling factor' of formed transmission line. According to philips' application note 'ESG89001' the coupling factor for a standard bi-layer PCB is about 0.6...0.9, where the coupling factor is the higher the wider the signal copper trace is.
A coupling factor of 0.6 means that about 40% of the signal return current will not run directly under the signal copper trace but will run freely over the PCB!
With mulitlayer PCB the coupling factor is about 0.9...0.97. So, less than 10% will finally run freely over the board.
This little estimation underlines how important it is to use a multilayer board, if very low noise levels are demanding. But even the mulitlayer board isn't perfect, if you compare the coupling factor with that of a RG-58 coax cable, which is 0.996.

Although this concentration mechanism for the ground return currents of high frequency signals is very impressive, there's no such mechanism for the voltage drop across ohmic impedance of ground plane. Means: If a high current is flowing across the ground plane between two arbitrary points, then the whole board is involved! So, while using an unsplitted ground plane for less noise sensitive analog signal conditioning might be acceptable, it might fail with high current applications.

Anyway with all this theory stuff: If you have a 16bit ADC application referring to 5V full scale, then the difference between two succeeding steps is 75µV (microvolt!). If you, dear Joseph, can guarantee me, that the ground potential difference between two arbitrary points on a board carrying fast digital chips will always be smaller than 100µV, then I will immediately stop using splitted ground planes. From this day on. Promised!

Kai