| ??? 03/12/05 02:03 Read: times |
#89519 - Many tolerate it, but some not! Responding to: ???'s previous message |
Craig said:
If the memory being accessed with screwy pinouts is being written to and read from by only the microcontroller, no translation is necessary since it will automatically be read out the same way it was written. Translation should only be necessary if the device is written by something that has the correct pin connections (such as an EPROM programmer) and is subsequently read by the microcontroller with an incorrect pin connection. Yes. In order to get unbroken buslines with bi-layer board I try to avoid making '1:1' connections, but 'scramble' the buslines. This even works for EEPROMs and their software write protection scheme. Here, of course, I have to translate the scrambled data, as Neil mentioned, means, I have to write different code bytes to different locations. This is more work, but as I can use the same scheme over and over again, this isn't any disadvantage. One relevant exception, where this 'scrambling' methode isn't allowed is bus routing to ADC and DAC converters, of course! Kai |
| Topic | Author | Date |
| WEOT: Inconvinient Pinouts. | 01/01/70 00:00 | |
| Cranky pin outs | 01/01/70 00:00 | |
| some like the mother, some the daughter | 01/01/70 00:00 | |
| Z80 family | 01/01/70 00:00 | |
| Not necessarily bad... | 01/01/70 00:00 | |
| It will work....... | 01/01/70 00:00 | |
| When and when not? | 01/01/70 00:00 | |
| RAM/EPROM | 01/01/70 00:00 | |
| Many tolerate it, but some not! | 01/01/70 00:00 | |
| inconvenient pinouts | 01/01/70 00:00 | |
| or thread between pins... | 01/01/70 00:00 | |
| Re: Living in past. | 01/01/70 00:00 | |
| the real question | 01/01/70 00:00 | |
| Errr...... probably | 01/01/70 00:00 | |
| Actually... | 01/01/70 00:00 | |
| erk | 01/01/70 00:00 | |
| Do you mean the package? | 01/01/70 00:00 | |
| package | 01/01/70 00:00 | |
| Max 7301 | 01/01/70 00:00 | |
| All in a days work. | 01/01/70 00:00 | |
FPGA pinouts | 01/01/70 00:00 |