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???
07/25/05 14:44
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 		 #98016 - no
Responding to: ???'s previous message
hi,

Slobodan Mandaric said:
... you get a completely wrong delay when register(s) start with 0 !

No, when both R6 and R7 are zero and you call LOOP_CYCLE then subroutine returns immediately without even one iterration.

Regards,
Oleg


List of 53 messages in thread
TopicAuthorDate
Pulse Width Modulation Code..giving back            01/01/70 00:00      
   Something else weird            01/01/70 00:00      
      Not Weird            01/01/70 00:00      
         Thanks, good to know.            01/01/70 00:00      
            hexmap, AT89C4051            01/01/70 00:00      
         To be more precise...            01/01/70 00:00      
   Delay ?            01/01/70 00:00      
      Other suggestions?            01/01/70 00:00      
         maybe            01/01/70 00:00      
            Timer ISR Pretty Long            01/01/70 00:00      
               Or simpler ...            01/01/70 00:00      
               not really            01/01/70 00:00      
   Ridicule            01/01/70 00:00      
   this may work!! try out...            01/01/70 00:00      
      Wrong !            01/01/70 00:00      
         my loop for >256 itterations            01/01/70 00:00      
            That's nice, but still ...            01/01/70 00:00      
               no            01/01/70 00:00      
   Using port read backs            01/01/70 00:00      
   Thanks... and some basic timer concepts            01/01/70 00:00      
      some answers            01/01/70 00:00      
         timekeeping            01/01/70 00:00      
            plerase quote everything            01/01/70 00:00      
               bloated ISR?            01/01/70 00:00      
                  This is a nice little bug that show up            01/01/70 00:00      
                     Yes but            01/01/70 00:00      
                        experience... or ....            01/01/70 00:00      
                           What is Erik's 8052 University?            01/01/70 00:00      
                              http://www.8052.com/forum/read.phtml?id=            01/01/70 00:00      
                     well            01/01/70 00:00      
                        Ah but...            01/01/70 00:00      
                        Is that a valid design criteria. Should            01/01/70 00:00      
                     use it later            01/01/70 00:00      
                        based on your post above that includes y            01/01/70 00:00      
                           Try it! (Curious myself) :-)            01/01/70 00:00      
         Still a bit confused            01/01/70 00:00      
            not quite complete            01/01/70 00:00      
               256 cycles            01/01/70 00:00      
                  youn are absolutotally missing the point            01/01/70 00:00      
                     Not a bug at all!            01/01/70 00:00      
                        which will not happen            01/01/70 00:00      
                           who's afraid of the wolf...            01/01/70 00:00      
                              crying wolf once bitten            01/01/70 00:00      
                                 you restriction...            01/01/70 00:00      
                                    Cynicism            01/01/70 00:00      
                                    more widespread among Pascal and C users            01/01/70 00:00      
                              Calculating machine cycles            01/01/70 00:00      
                                 Counting machine cycles            01/01/70 00:00      
                                 Use Keil or JSIM tools            01/01/70 00:00      
                                 the point            01/01/70 00:00      
   PWM with 8051            01/01/70 00:00      
      Some debugging is required            01/01/70 00:00      
NOTICE: Message(s) moved            01/01/70 00:00      

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