??? 09/19/05 14:12 Modified: 09/19/05 14:15 Read: times |
#101226 - To Mike! Responding to: ???'s previous message |
Mike said:
As I interpret it, the "Stop" signal should have SDA going from low to high while SCL is high. .... .... Forgive me if I use the wrong terminology of high and low. I just base it as looking at the schematic of the signalling in the appnote. Which should leave SDA and SCL high after the signal, but the code has SCL being low. Hi Mike agian As you see in I2c_Stop Routine while scl is high a low to high is happened for sda,But about clearing scl i must say it is my method for applying any timing,so you can delete clr scl in your code, I2C_STOP: ;end of i2c routine SETB SCL CLR SDA SETB SDA CLR SCL RET anyway you can test and simulate this code in to pinnacle 52 for some i2c device sush as ds1803,ds1307,24cxx Good Luck Mehdi |
Topic | Author | Date |
Using IIC.ASM | 01/01/70 00:00 | |
address, speed | 01/01/70 00:00 | |
Yes | 01/01/70 00:00 | |
two things | 01/01/70 00:00 | |
Is HW I2C easier? | 01/01/70 00:00 | |
That may have been true then, this is no | 01/01/70 00:00 | |
Replies. | 01/01/70 00:00 | |
Check SBCMON | 01/01/70 00:00 | |
SBCMON | 01/01/70 00:00 | |
try a serial memory | 01/01/70 00:00 | |
let us try another tack | 01/01/70 00:00 | |
another tack. | 01/01/70 00:00 | |
you have created just about the worst co | 01/01/70 00:00 | |
Worst conditions. | 01/01/70 00:00 | |
oscilloscope | 01/01/70 00:00 | |
oscilloscope | 01/01/70 00:00 | |
To verify that your programming ("burnin | 01/01/70 00:00 | |
verifying. | 01/01/70 00:00 | |
Without a scope you are kind of stuck, s | 01/01/70 00:00 | |
Success.![]() | 01/01/70 00:00 | |
back to the roots | 01/01/70 00:00 | |
Success. | 01/01/70 00:00 | |
To Mike! | 01/01/70 00:00 | |
Hello Mehdi | 01/01/70 00:00 | |
Or... | 01/01/70 00:00 | |
this is a bootleg, use the original | 01/01/70 00:00 | |
i2cbits | 01/01/70 00:00 | |
you may want to go here | 01/01/70 00:00 | |
Clock width is only 2 uSec in IIC_ASM ex | 01/01/70 00:00 |