| ??? 06/20/06 17:05 Read: times |
#118628 - DMA! Responding to: ???'s previous message |
Richard Erlacher said: What a pity; I'd have a suggestion or two... :-)))
No, Jan, I have no intention of building yet another 805x chip. Richard Erlacher said:
With cores capable of far-exceeding the speed at which SRAM can operate, and, certainly exceeding the rate at which FLASH memory can supply code, I see no particular benefit of providing DMA. DMA would involve a considerable amount of logic, specifically, logic that would slow down the operation of the entire core. If a user wants/needs to use DMA he should use an ARM or other commercially available core that is designed to support it. No, no, no. I doubt you'd be able to access SRAM (read: data memory) at a rate that would make the SRAM completely busy. And, a software interrupt-based etc.etc. solution to keep the UART busy cannot be superior to hardware solution, by no means. The DMA access would be quite transparent to the '51, and even if it would slow down the core, it is certainly far less than a software-based data handling routine. It might even be a not-so-true-DMA, the DMA controller might be the one who waits if the SRAM is busy - for serial transfer it won't make a change (and it might buffer up 1 character easily) - then there is NO speed penalty for the '51. The idea is complete lazyness (and that appeals to me) - you prepare your data, write a couple of registers in the DMA controller and FORGET IT, the slave makes the dirty job for you. No more ri/ti... :-))) Have fun! Jan Waclawek |
