First of all, forget about the UART(s) that appear in "standard" 805x's.

It's true that the stupid, Stupid, STUPID way in which Intel designed this chip's serial I/O, back when nobody knew better, prevents the use of the serial I/O channel in Mode 0 for anything synchronous, which was probably because nobody cared, since MCU's weren't fast enough to do it any better back then. However, we're no longer limited by the technological limits of 30 years ago. We're foolish, in fact, not to use what's available today, so I'm asking you to either to consider an 805x core without the "standard" timer/counter(s) and without the "standard" serial ports. Think, instead, of an 8031 CPU core with 64KB of data space, 64KB of code space, the "standard" 128 bytes of conventional scratchpad memory and the "standard" 128 bytes of conventional SFR space, but with the SFR's totally undefined. I'm not even sure I want to commit to providing that other, indirectly addressable 256 bytes of RAM, though I guess that could be done easily enough. I'm just thinking that, since the code will be compiled, assembled, linked, and loaded before the hardware is constructed, it needn't have even one byte more than is required, and since it will not matter whether the RAM is XRAM or internal, there may not be a justification for the overlapping memory spaces at 0x80..0xFF. I'll provide it if it's convenient, but it may be one of the first things to go. We'll see ...

Now, I'm not hostile to the present SFR setup if the associated features are present. However, I see no point in using up valuable I/O space for features that are not using them.

RE