since all the RAM is internal, and since I can control the configuration (width, depth), I can, potentially, access more than one byte at a time. Further, since the RAM is entirely internal, I can also access it in one cycle, irrespective of whether it's IRAM or XRAM. None of that will have any impact on the instruction set, though it will impact the instruction timing.

Likewise, if I always have a 48-bit (possibly fewer bits) wide window into both code and data space open, I can load the DP in one stroke and read/write the associated memory content on the next. What's more, since source and destination are open at the same time, a transfer between them takes only one cycle.

I've not yet determined which sort of approach will be the most satisfactory, but the options are plentiful. That's off topic, though. I'm after the advantages/disadvantages of changing the SFR's for peripherals that are not included. True, few people use mode-0, for example, but if the firmware could select the direction of the shift, and would not require explicit clearing of that interrupt bit, it could be quite useful. Perhaps an added CRC generator/checker would help, too, since parity is of little use in efficient communication.

RE