... that's just stupid me.

I thought, if the micro never goes to data memory, there is no collision with DMA hence no impact on its performance. I'd expect buffers between internal buses and external data memory buses anyway. But let's leave this for now - you probably know far better than me.

One last word, one can also make a dedicated piece of memory (with separated data+address bus) only for the UART/DMA, but that's then called FIFO :-)))




I was under the impression you are going to design a super-'51, sub-one-clocker, out-of-order-execution and all that advanced stuff; in that case I believe you'd also solve the notorious limited stack problem and add also a bunch of RAM. Where's the limited resources mcu now? :-)))

No, I don't need to convince anybody, that's just that lazy me, if there is a way how to do the job doing nothing, I take it... :-)))

Have fun!

JW