??? 06/21/06 16:58 Read: times |
#118773 - I looked at them years ago Responding to: ???'s previous message |
and, yes, they're gone. I think the pricing killed 'em.
A hard core in an FPGA is really only of use when the "whole shootin' match" can be shoehorned into a single FPGA. XILINX has Power PC and their own "MicroBlaze" MCU in their Virtex series of FPGA's. Those are costly, however, and when one prices out a costly FPGA with an internal core vs. a lower-cost FPGA with an external MCU, there's got to be a really compelling reason to use the internal core or the technology that contains it. Normally those VIRTEX devices are used by people who need the high-speed technology for the multi-Gb serdes or other high-speed application, and, since the core's there, they use it. With Triscend's 805x core, it was too costly to use in place of a physical 805x chip and a cheaper FPGA, so it was hard to sell. Their core licenses were not cheap either, so they went the way of the Dodo bird ... My interest in developing this core is not to enable people to reuse code they've already developed, though that's not ruled out. I'm wanting to use the 805x core because the software tools support its instruction set. The software tools only produce a binary code set that cares not how long an instruction takes to execute. It also cares not how wide the instruction word is. So, it's conceivable that a hardware lookup could determine how many bytes of code are needed to make the current instruction work in one stroke and then do that. It also could determine whether the next instruction can be executed in parallel with the current one, or two, e.g. a MOV A,#055H followed by MOV DPL,#065h, followed by MOV DPH,#010H, could all be concurrently executed, given the appropriate configuration. These FPGA's have TONS of logic available. I've got to explore how best to use it. Trust me, though, when I say that the design and development of the hardware will not be the most difficult part of this operation. The development of the software tools that will seamlessly allow integrating the various independently generated peripherals into the FPGA and will produce the needed headers and includes so that standard tools will still support the thing will be the most "interesting" (meaning I hope someone else will do it) part. RE |