The TTL databook doesn't show pullups on the inputs of the LS573's nor does it show them for the '373's. That's all moot, since my circuit is wired for '573's and I've got only one LS573 in house. I suppose I could plug in a shorting header in the 20-pin site where the P2 latch lives ... but I probably won't do that.

You're entirely correct about the voltage levels. I find these HMOS parts drive their outputs to within a few millivolts of the positive rail with just the CMOS latch on their outputs, and they do it very fast with very fast rise/fall times.

BTW, I keep runing into the reasons why I never learned to like this family back when they were new. They are so slow for the logic technology. The address is valid two clocks before nPSEN, which I find to be a very generous allowance.

I'm glad the pullups aren't a factor. I can leave them out, as I always intended to do.

BTW, are you sure about that 500 ns? I'd guess it's closer to 50, in theory, though what I'm seeing suggests it's well under 5. I have two memory devices on the data bus, and they're in four sockets, i.e. both wide and narrow sockets for the RAM and PROM (I have a CY7C261-55 as an alternative EPROM) so the individual signal paths are quite long (~15 cm or so).

RE