??? 02/05/07 05:44 Modified: 02/05/07 06:08 Read: times |
#132000 - You\'re looking in the wrong place Responding to: ???'s previous message |
at least for the solution to your etching problem. Did you agitate the solution while the board being developed was in it? It probably needs CONSTANT agitation, and CONSTANT temperature control, else you wouldn't get uneven development as you apparently have.
Secondly, I don't see what relevance jedec compatibility has to the business of board layout or circuit function. The addresses on the standard DIP-40 803x/5x are arranged such that D0/A0 alre located at one end of one side of the package, and A8 is located at the other. Both progress inward, with ALE, which controls the address latch that's normally attached to P0 (pins 39..32) in what would probably be the most convenient location for it. nEA is located between the two ports also, as it's convenient as an output enable for the address latch. If you locate your 74HC573 address latch near pins 39 down to 32 you can then connect them directly to pins 2..9, connect pin 31 (nEA)to pin 1 by routing it between the MCU pins 39 and 40, and route pin 30 directly to pin 11, the latch enable on the '573. pin 29 can then be routed between that combination and the external PROM's output enable, which wants to be driven with nPSEN. It's actually a very convenient pinout. If you're using DIP-40, then you should have no trouble with 0.5 mm and from what I guess you'r doing, it would be best if all your tracks are the same width until you learn exactly how to control temperature and to agitate properly so none of your traces are over- or under-etched. Whta size and shape pads are you using? For starters, round pads would probably work best, and, as mentioned before, until you get a good handle on what affects over- or under-etching, you probably should use vias the same size, by means of which to place jumpers where you couldn't route the traces. How are you distributing power? Which package are you really using? Are you using two-sided material with one side as ground plane? Please start by explaining the importance of the jedec standard in what you're doing, though, particularly as it impacts you, because I really don't see that it limits you in any way, or, for that matter, is even relevant. RE |