??? 02/05/07 13:26 Read: times |
#132028 - I explain Responding to: ???'s previous message |
I haven't made it to the etching stage. I failed at the developing stage. And how can overexposure make the board fail?
My pads are 1.2mm in diameter (circles) with 0.65mm holes for drilling. The big problem is optimal arrangement, especially arranging an 8K RAM (CY7C-185), and a 32K EEPROM (atmel AT28C256) to an 8051 microcontroller (intel 80C51-BH) The RAM and ROM has a write pin at #27, a read pin at #22 and a chip enable pin at #20. All of these pins are considered enabled when logic low is applied. The problem I seem to have is that all of the control pins are between the data and address pins of all devices, which makes interfacing a problem. Also, it seems to me that it is more optimal to reverse the ram and rom so VCC is on the opposite side, but I'm a little lost. I'm also using a single sided photo resist covered board. |