Well...

It looks like he is trying to do logical minimisation:

His ROM basically does this kind of translation:

Num.- Addr inputs - Data outputs (instr.)   -

No. | A B C D E F | b7 b6 b5 b4 b3 b2 b1 b0 |
----+-------------+-------------------------|
  0 | 0 0 0 0 0 0 | x  x  x  x  x  x  x  x  | <- instruction byte0
  1 | 0 0 0 0 0 1 | -  -  -  -  -  -  -  -  | <- instruction byte1
  2 | 0 0 0 0 1 0 | +  +  +  +  +  +  +  +  | <- instruction byte2
 ...
 63 | 1 1 1 1 1 1 | *  *  *  *  *  *  *  *  | <- instruction byte63
----+-------------+-------------------------+

Now, he need to do logical minimisation to get functions for outputs as a function of inputs, eg:

f0: (A,B,C,D,E,F)->b0,
f1: (A,B,C,D,E,F)->b1,
...
f7: (A,B,C,D,E,F)->b7

or, more convenient way of writting it: f0(A,B,C,D,E,F)=b0 e.g. f0 translates input (address) vector to output (instruction bit0). Trick is to find neccessary f0.

He can opt whether function f has structure of SUM(PRODUCTS) or PRODUCT(SUMS) based on his target base (nand/nor) and structure of his table (minimise over '0' or over '1'). Since minimisation by hand is tedious work, he opted to use automated process QM. In his previous post, he just said that as a result of minimisation he got:
So, if you assume that his function is SUM(PRODUCTS) then his writeout should mean:

f0=(F and (not)D and (not)C and B and A) or (F and (not)E and (not)D and B and A) or ...

which means that his bit0 of resulting intruction byte can be realised as combinational matrix or above mentioned and, or and not operations over input address bits (A,B,C,D,E,F).

And he needs no 8-bit buffers (combinational matrix is sufficed, no sequential elements required to build ROM) to do so, what he migh have as a problem is maximum number of gates per output and propagation delay problems.

I still think, as I've said im my previous post, that it is wrong way to go about things and why.

Best luck,
CN