Mike:

Your idea to implement a hardware solution for a 64 instruction "program" to implement the programming algorithm in your microcontroller is a kind of a zany idea at best as you have read from all the responses that have come to this thread. That said however do know that this is technically possible but not really particularly practical in the way that you have indicated that you wish to implement it.

I cannot comment much on the legitimacy of the small program that you presented as a valid scheme to program an EEPROM. The code seems to be based upon the fact that you could write into the EEPROM from address zero, byte by byte, with no other type of handshaking or timing constraint. But be that as it may this does create a program that is a little shorter than the 64 bytes that you have been talking about. I put the actual program together as a "source file" and fed it through the Keil Assembler/Linker process to produce a normal HEX file of the program data.

You can view this source code by clicking here: Source Code

The resulting HEX file of data somewhat re-formatted can be seen here: Object Data

I got interested to see just how much minimized logic it would take to produce the logic equivalent of a 64-byte ROM. So I installed the Xilinx CPLD/FPGA device compiler and drew up a schematic that uses a brute force batch of MUXes to select 1's and 0's for each of the eight data outputs based upon the address inputs. I limited the address inputs to A0 to A5 since six bits can select 64 of the locations in the CrazyROM. I based the 1's and 0's for the "program" based upon the compiler output that is linked above. You may see a PDF of the schematic here: CrazyROM Schematic File

Placing this into the Xilinx tool set in this manner allows me to take full advantage of the logic mimimization capabilities of the program and be reasonably assured that the minimized equations do indeed correspond to the data input via the schematic. (Do note that other forms of input to the tool set may have been a better choice but I chose schematic since it parallels your desire to build this with logic gates). The Xilinx tool set produced the set of equations that you may see at this link: set of equations Notice that these equations do show a tristate buffer output enable on the CrazyROM outputs. This may be needed to permit the "ROM" hardware to be managed on the bus of the microcontroller to avoid contention with the normal EEPROM and RAM chips that you indicated that you intend to also have on the circuit board.

My estimate in looking at these equations is that it would take maybe 35 to 45 logic chips of the 14 and 16-pin variety to implement these equations. That is quite a few. And would be a major pain if you find that the "original" program needs to be changed just after you get this thing all built. On the other hand if you look at the equations closely it can be seen that these would fit with ease into a PAL or GAL 22V10 type part. The Xilinx tool set suggested a fit into a small 44-pin CPLD part in their 9500 family.

I think this shows that there are several considerations that need to be made here. Foremost is that the CrazyROM can be implemented in one chip (i.e PAL, GAL, CPLD) or even a small 64-byte PROM as others here have suggested. That consideration itself should be enough to show you that the handfuls of logic chips is not a good way to go with this. The other consideration is that good engineering judgement, practice and tradeoffs should be applied when looking at this problem.

I have gathered all the materials for the program and the Xilinx project files together into a single ZIP file should you want to try to use the Xilinx tool set to minimize your logic. ZIP File (858K)

Good Luck. (Oh by the way .... go buy yourself an in-system programmable FLASH based microcontroller. Use it once and you'll wonder why this thread even exists).

Michael Karas