??? 02/12/07 14:51 Read: times |
#132622 - Nothing critically timed ... Responding to: ???'s previous message |
Lynn ... Wouldn't it work OK to create that 'E' clock by setting ALE on ALE, then clearing it when it's set or when (/nWR+/nRD) occurs? The pulse width could be adjusted with a couple of Flipflops. It's not a critical parameter, though it must occur during each access cycle, and the hardware to generate it would easily fit in a small PLD.
You're right, in that the INIT cycle might prove to be be a pain, but even you were talking about a well-too-slow version of the 82C55 ... I just happened to be looking at a box of HC11 boards ... They seemed to like that 68HC24. The HC11 doesn't handle the HC24 in hardware, though it does pass parameters during the INIT cycle. RE |
Topic | Author | Date |
port expander ... NOT 82C55! | 01/01/70 00:00 | |
have not, but how about a link | 01/01/70 00:00 | |
Link... | 01/01/70 00:00 | |
Not so fast with the TK68HC24 | 01/01/70 00:00 | |
Nothing critically timed ... | 01/01/70 00:00 | |
Generation of "e" clock | 01/01/70 00:00 | |
inserting a square peg in a round hole | 01/01/70 00:00 | |
Yes, it requires tools to make it fit ... | 01/01/70 00:00 | |
The reason for 2 ALE cycles | 01/01/70 00:00 | |
Too bad they weren't smarter ... | 01/01/70 00:00 | |
Pipelining in the 8051 | 01/01/70 00:00 | |
It\'s possible in some cases ... | 01/01/70 00:00 | |
technology marches on | 01/01/70 00:00 | |
Those Dallas 4-clockers date back to ~1992 or so![]() | 01/01/70 00:00 |