| ??? 02/13/07 00:27 Modified: 02/13/07 00:28 Read: times |
#132703 - It\'s possible in some cases ... Responding to: ???'s previous message |
Were I to build-from-scratch, in FPGA, for example, I'd make the rom very wide and get lots of lookahead options that way, enabling me to execute 3-byte instructions in one cycle, and, in some cases, execute some instructions out of order and some in parallel.
Once "they" went to major internal code space, that option was open to "them." I've looked at that at some length and believe that it's possible to achieve 100 MIPs at 50 MHz by using that approach. One of these days ... and my verison won't have that stupid positive-reset. RE |
| Topic | Author | Date |
| port expander ... NOT 82C55! | 01/01/70 00:00 | |
| have not, but how about a link | 01/01/70 00:00 | |
| Link... | 01/01/70 00:00 | |
| Not so fast with the TK68HC24 | 01/01/70 00:00 | |
| Nothing critically timed ... | 01/01/70 00:00 | |
| Generation of "e" clock | 01/01/70 00:00 | |
| inserting a square peg in a round hole | 01/01/70 00:00 | |
| Yes, it requires tools to make it fit ... | 01/01/70 00:00 | |
| The reason for 2 ALE cycles | 01/01/70 00:00 | |
| Too bad they weren't smarter ... | 01/01/70 00:00 | |
| Pipelining in the 8051 | 01/01/70 00:00 | |
| It\'s possible in some cases ... | 01/01/70 00:00 | |
| technology marches on | 01/01/70 00:00 | |
Those Dallas 4-clockers date back to ~1992 or so | 01/01/70 00:00 |