| ??? 02/12/07 23:17 Read: times |
#132694 - The reason for 2 ALE cycles Responding to: ???'s previous message |
Richard said I don't know why Intel had to put out two ALE cycles per code-space access ... Intel needed to fetch the second byte of the operand before the first one was decoded, just in case the opcode had two bytes. If it turned out that the opcode was a single byte, then the second fetch was ignored. |
| Topic | Author | Date |
| port expander ... NOT 82C55! | 01/01/70 00:00 | |
| have not, but how about a link | 01/01/70 00:00 | |
| Link... | 01/01/70 00:00 | |
| Not so fast with the TK68HC24 | 01/01/70 00:00 | |
| Nothing critically timed ... | 01/01/70 00:00 | |
| Generation of "e" clock | 01/01/70 00:00 | |
| inserting a square peg in a round hole | 01/01/70 00:00 | |
| Yes, it requires tools to make it fit ... | 01/01/70 00:00 | |
| The reason for 2 ALE cycles | 01/01/70 00:00 | |
| Too bad they weren't smarter ... | 01/01/70 00:00 | |
| Pipelining in the 8051 | 01/01/70 00:00 | |
| It\'s possible in some cases ... | 01/01/70 00:00 | |
| technology marches on | 01/01/70 00:00 | |
Those Dallas 4-clockers date back to ~1992 or so | 01/01/70 00:00 |