| ??? 02/12/07 23:31 Read: times |
#132697 - Too bad they weren't smarter ... Responding to: ???'s previous message |
They could have pipelined the thing, adding a couple of prefetch registers so they could avoid that. The result is that code memory has to be twice as fast. No wonder the original was so slow (1 MIPS).
Too late now ... RE |
| Topic | Author | Date |
| port expander ... NOT 82C55! | 01/01/70 00:00 | |
| have not, but how about a link | 01/01/70 00:00 | |
| Link... | 01/01/70 00:00 | |
| Not so fast with the TK68HC24 | 01/01/70 00:00 | |
| Nothing critically timed ... | 01/01/70 00:00 | |
| Generation of "e" clock | 01/01/70 00:00 | |
| inserting a square peg in a round hole | 01/01/70 00:00 | |
| Yes, it requires tools to make it fit ... | 01/01/70 00:00 | |
| The reason for 2 ALE cycles | 01/01/70 00:00 | |
| Too bad they weren't smarter ... | 01/01/70 00:00 | |
| Pipelining in the 8051 | 01/01/70 00:00 | |
| It\'s possible in some cases ... | 01/01/70 00:00 | |
| technology marches on | 01/01/70 00:00 | |
Those Dallas 4-clockers date back to ~1992 or so | 01/01/70 00:00 |