Hmmmmm....

We had recently a very serious problem with a '51 controller reset.

It was a PSU controller (once again) who sometimes fired a FET at the very beginning of the POR with catastrophic consequences.

It appeared that the problem was due to a slowly starting clock which caused the chip internal reset sequence to delay by time that was in millisecond class. The outputs are defined to be in the so called "weak pullup" state when reset is active BUT this is only AFTER the internal reset sequence has done it's thing. And this of course is once again dependant on the brand, version and general attitude of the chip manufacturer. Maybe it is also affected by mood phase and air pressure - who knows.

The solution was to gate all outputs so that when reset was active no FET firing could happen.

I just told this to tell You that any discussion about reset timing is irrelevant unless the entire circuitry and the application where the chip is used is known.

I always take the reset input before the regulator so that the reset condition goes away only when there is enough juice BEFORE the regulator. This is a good solution because the tolerances at that side are very russian as compared to the regulated (5V, 3.3V ...) side. You also give the CPU a chance to float itself before the VCC actually vanishes.

In most cases a simple capacitor serves just fine as a reset circuit.

The maximum deviation from VCC (or VDD) is about 0.8 volts when a PNP transistor is properly connected to "invert" the reset. I did NOT suggest using a logic gate since those have an undetermined state when operated outside their specs. The MTBF of an ordinary bipolar bjt is hig enough to be neglible.