| ??? 12/04/07 19:21 Modified: 12/04/07 19:22 Read: times |
#147861 - How to use a rest chip properly Responding to: ???'s previous message |
Esko said:
We had recently a very serious problem with a '51 controller reset.
It was a PSU controller (once again) who sometimes fired a FET at the very beginning of the POR with catastrophic consequences. It appeared that the problem was due to a slowly starting clock which caused the chip internal reset sequence to delay by time that was in millisecond class. The outputs are defined to be in the so called "weak pullup" state when reset is active BUT this is only AFTER the internal reset sequence has done it's thing. And this of course is once again dependant on the brand, version and general attitude of the chip manufacturer. Maybe it is also affected by mood phase and air pressure - who knows. I would use a MAX1232 in combination with a micro providing an asynchronous port reset, while not using the internal supervisory section and watchdog. Let the MAX1232 do that job, it's brilliant and much better than this internal stuff (tighter thresholds, hysteresis and less noise). Esko said:
I always take the reset input before the regulator so that the reset condition goes away only when there is enough juice BEFORE the regulator. This is a good solution because the tolerances at that side are very russian as compared to the regulated (5V, 3.3V ...) side. You also give the CPU a chance to float itself before the VCC actually vanishes. I cannot see any advantage of this methode. Or do you mean the generation of an "early power fail interrupt", as an additional reset feature? A reset chip makes only sense if it carefully monitors Vcc, means the supply voltage of microcontroller. The voltage at input of regulator is entirely irrelavant, unless you want to use it as "early power fail interrupt", as already mentioned. Esko said:
In most cases a simple capacitor serves just fine as a reset circuit. No, not for Flash micros!! It's reported many times, that an unreliable reset can corrupt the code if it residues in a flash memory that can be altered by the micro itself (ISP-programming, for instance). Esko said:
The maximum deviation from VCC (or VDD) is about 0.8 volts when a PNP transistor is properly connected to "invert" the reset. An additional PNP hardly makes trouble when Vcc is at nominal voltage. But when Vcc falls, then at a certain moment, the reset chip will no longer be capable to control your PNP, because the drain cource channels of internal PMOS- and NMOS-FETS become extremely high ohmic. As result, your reset scheme will hardly work down to Vcc=0V, which is no problem for a good reset chip, on the other hand. Kai |
| Topic | Author | Date |
| Is this a problem with some reset supervisors? | 01/01/70 00:00 | |
| Precisely! | 01/01/70 00:00 | |
| Wrong direction | 01/01/70 00:00 | |
| most of the time... | 01/01/70 00:00 | |
| I will test the series resistor solution | 01/01/70 00:00 | |
| this does not make any sense | 01/01/70 00:00 | |
| "push-pull" output, MCP101 | 01/01/70 00:00 | |
| sorry, have not done that one for a while | 01/01/70 00:00 | |
| NO, it is NOT | 01/01/70 00:00 | |
| Exactly! | 01/01/70 00:00 | |
| first part is wrong, second is right. | 01/01/70 00:00 | |
| 8051 related reset stuff with external components | 01/01/70 00:00 | |
| How to use a rest chip properly | 01/01/70 00:00 | |
| Advantages | 01/01/70 00:00 | |
| Not so fast, there, Pilgrim ... | 01/01/70 00:00 | |
| I have given up to convince you | 01/01/70 00:00 | |
It's not just you, Kai ... | 01/01/70 00:00 |