The ISP programing circuit for the DS89C4x0 involves, aside from the MAX232, three tristate buffers that directly drive nEA, RESET, and nPSEN. How did that come to be on the 8052SBC?

My DS89C420s DS89C430's and DS89C450's have all behaved just as I expected insofar at they could in the context of being fast 8032's. I'vc not yet attempted to use the internal FLASH, though.

I have found, through experimentation, that they work just fine in "Page Mode 1" with external memory, at 50 MHz. That's the speed at which they were advertised to run back when the DS89C420's were first promoted. By 2002, that had been downgraded to 33 MHz, because the internal flash wouldn't operate at that speed. I've cursorily verified that the internal XRAM would operate at that speed, also, but have not yet verified that it would actually work as code space, a feature which is offered in the DS89C4x0's. Of course, if the internal logic is capable of that sort of performance, then there's no reason why one couldn't exploit that in an extreme case in which a small (<1KB) segment of code could be assembled for and loaded into that space, and it mapped into code space. These devices have numerous memory-mapping and internal/external bus timing options not so common on other MCU's.

RE