Even the Dallas EVK didn't support all the available options that their MCU provides. It's really thoughtful that you did provide the necessary features to support the ISP of the Dallas chips. I've yet to see one that does, frankly.

Since pike to I use a CPLD to replace the address latches and support logic, it's easy to incorporate features like the extra latches to support the address demultiplexing modes that Dallas put into these devices that others didn't. Page Mode 1 uses P2 for both high and low addresses, with data on port 0, while Page Mode 2 uses P0 for the low addresses with data and high addresses on P2. That, in discrete logic, would require an extra '373 and an extra '245 to make all the options available, and, of course, it would demand, too, that there be some steering and control logic to concatenate them in the appropriate way.

Once you have a piece of programmable logic in the picture, it becomes simple.

Since any arrangement requires that nEA be steered between high and low, depending on whether one is using internal or external program, and since reset has to be controlled in a way that's compatible with the DS89c4x0's bidirectional reset signal, it's easiest to manage all that in programmable logic. The MCU guys at Dallas, in 1999 or so, told me it should be done with a bus switch, but I found the extra '373 and '245, somewhat less costly. That may no longer be the case, of course, but that was then ... Of course, the Dallas people then claimed their MCU worked at 50 MHz. That turned out to be disappointingly untrue.

What's really cool about the programmable logic approach, is that one can dump an EPROM into SRAM and then disable the EPROM, leaving the much faster SRAM as the primary external program store, which is very capable of operating at speeds greater than the internal FLASH. Now that the DS89C450 is available, one can do that in order to have an extra program store available. It's not often helpful, but when it is ...

RE